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SUMMARY:Green Cache - Erik Hagersten\, Uppsala University
DTSTART:20180426T130000Z
DTEND:20180426T140000Z
UID:TALK104170@talks.cam.ac.uk
CONTACT:Timothy Jones
DESCRIPTION:*Abstract*\n\nTraditional caches tightly couple data with thei
 r metadata in the form of address tags. The location of a requested datum 
 is determined by hierarchical searches\, in which many address tags (≈th
 e cache associativity) at each cache level are compared to the requested a
 ddress to answer the question\, Is the datum here? The address tags of dat
 a being evicted also need to be searched\, to cover coherence-corner cases
 . The hierarchical searches add both energy and latency overhead to memory
  accesses.\n\nGreen Cache is a new\, efficient and simple coherent cache a
 rchitecture that relies on a new kind of metadata\, cacheline pointers (CP
 )\, that answer the question\, Where is the datum? CPs encode the location
  of the requested data (in which cache? in which associative way?) in fewe
 r bits than address tags (≈6 bits vs. ≈30 bits). CPs are not coupled t
 o their corresponding data\; instead\, CPs are stored in a small\, separat
 e metadata hierarchy that makes it likely that a core will find the CP for
  a requested datum in its small\, private metadata cache (e.g.\, the reque
 sted datum is in associative way seven of the LLC slice adjacent to core t
 hree).\n\nBy introducing delayed acknowledges\, the coherence protocol of 
 Green Cache makes the CP information deterministic\, guaranteeing that the
  requested datum remains in its identified location when the request for i
 t reaches that location. This removes many traditional coherence corner ca
 ses and allows the data caches to be implemented by a plain SRAM array –
  with no address tags or comparators\, just a simple SRAM read. Its cohere
 nce protocol also automatically classifies private data\, thereby removing
  90% of the traditional directory traffic\, and offers flexible data place
 ment\, enabling cheap cache bypassing and non-uniform cache architecture t
 opologies (NUCA). Green Cache reduces the traffic in the memory hierarchy 
 of a mobile processor by an average of 70%\, reduces its dynamic energy (i
 n EDP) by 50% and reduces its latency for L1 cache misses by 30% across a 
 wide selection of benchmarks.\n\n*BIO*\n\nErik Hagersten has held a profes
 sor chair in computer architecture at Uppsala University in Sweden since 1
 999. Prior to this\, he was the chief architect for Sun Microsystem's high
 -end server engineering division in the US 1993-1999. In 2006 he founded A
 cumem AB\, developing new modeling technology  for multicore software opti
 misations. Acumem was acquired by Rogue Wave Software Inc. in 2010. Since 
 2014 he is the CEO of his second startup\, Green Cache AB.\n\nAt Uppsala\,
  Erik has built up he Uppsala Architecture Research Team\, UART ("group pa
 ge":http://www.it.uu.se/research/group/uart) – one of the largest archit
 ecture research groups in Europe. UART performs research in fast performan
 ce modeling technology\, compiler technology as well as more traditional c
 omputer architecture topics\, with an emphasis towards energy-efficiency.\
 n\nHe is a member of the Royal Swedish Academy of Engineering Sciences (IV
 A) since 2002 and received the most prestigious research award of Uppsala 
 University 2013 (The Björkénska award).
LOCATION:FW26\, Computer Laboratory\, William Gates Building
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