Abstract

Title: Availability, Integrity, and Confidentiality in a Content Centric Internet Architecture

Presenter: Mohibi Hussain, Systems Research Group

Abstract

“How can we integrate security by design in a Content- Centric future Internet architecture to ensure availability, integrity, and confidentiality ?” The current Internet infrastructure, initially conceived to provide closed group connectivity to a limited user-base, is now facing the challenges of catering to over three billion users with dynamically changing data, transport, and access requirements. Named-Data Networking (NDN) which is an example of Information Centric Networking (ICN) or Content-Centric Networking (CCN), is being explored as a possible future Internet architecture. Given the important challenges of availability, integrity, and confidentiality in the ever-changing information security landscape, it is imperative to build NDN with intrinsic resilience based on the security by design narrative. We have explored DDoS mitigation as a defence mechanism to improve availability, content poisoning cure to ensure integrity, and name obfuscation for privacy and confidentiality in NDN . Modelling the non-functional requirements for NDN through system dynamics completes the story by catering for the essential external variables affecting the design of an Internet architecture.

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Title: Reducing the overhead of Parallel Loop Schedulers for Many Core Processors

Presenter: Mahwish Arif, Computer Architecture Group

Abstract

While Moore’s law remains active, every new processor generation has an increasing number of cores. The multi/many-core shared memory machines offer opportunity for increased intra-node parallelism and thus performance improvement for the applications. However, the higher core count also poses challenges to schedule and distribute work load on these cores in a timely and scalable manner. My research aims at improving the scalability of parallel loop schedulers by specialising them for fine-grain loops. To this end, we propose a low overhead NUMA -aware work distribution mechanism for a static scheduler. We integrate this static scheduler with the Intel OpenMP and Cilkplus parallel task schedulers to build hybrid schedulers. Detailed, quantitative measurements demonstrate that our technique achieves scalable performance on a 48-core machine with significantly lower overhead than both Intel OpenMP and Cilkplus. We demonstrate consistent 16-30% performance improvements on a range of HPC and data analytics codes, with a peak at 2.8x.

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Title: Energy Efficient In-Memory Approach for Binary Convolutional Neural Network

Presenter: Aida Miralaei, Computer Architecture Group

Abstract

One of the most effective methods for reducing the inference cost of neural networks is to reduce the precision of computation. Quantizing or binarizing network weights and activations reduces the precision of arithmetic operations in a CNN , but will effectively reduce the power consumption. Moreover, computations in CNNs with binary weights and activations have a very good potential to be simplified into bitwise operations which can make them more energy efficient. In this talk, I’ll show how implementing the computations of BCN Ns’ inference phase in the main memory helps the system to benefit a significant performance gain and energy saving. Then I’ll talk about the proposed architecture of my design and how I can take advantage of the processing-in-memory implementation of inference phase of BCN Ns to accelerate the computations and reduce energy consumption.