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CATEGORIES:CAS FPGA Talks
SUMMARY:An FPGA-based Implementation of the MINRES Algorit
 hm - David Boland\, Imperial College London
DTSTART;TZID=Europe/London:20080805T113000
DTEND;TZID=Europe/London:20080805T121500
UID:TALK12801AThttp://talks.cam.ac.uk
URL:http://talks.cam.ac.uk/talk/index/12801
DESCRIPTION:Due to continuous improvements in the resources av
 ailable on FPGAs\, it is becoming increasingly pos
 sible to accelerate floating point algorithms. The
  solution of a system of linear equations forms th
 e basis of many problems in engineering and scienc
 e\, but its calculation is highly time consuming. 
 The minimum residual algorithm (MINRES) is one met
 hod to solve this problem\, and is highly effectiv
 e provided the matrix exhibits certain characteris
 tics. This paper examines\nan IEEE 754 single prec
 ision floating point implementation of the MINRES 
 algorithm on an FPGA. It demonstrates that through
  parallelisation and heavy pipelining of all float
 ing point components it is possible to achieve a s
 ustained performance of up to 53 GFLOPS on the Vir
 tex5-330T. This compares favourably to other hardw
 are implementations of floating point matrix inver
 sion algorithms\, and corresponds to an improvemen
 t of nearly an order of magnitude compared to a so
 ftware implementation.
LOCATION:Mahanakorn Laboratory\, EEE
CONTACT:Dr George A Constantinides
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